In this example, an efficient approach for DTCO is demonstrated which combines parasitics extraction (PEX), BSIM model card calibration, and SPICE simulations of a 6T-SRAM cell employing CFET A5 technology with pMOS pass-gates.
Project Name: DTCO_CFET_A5_Spice_SRAM
PDF revision of 17 September 2024
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